1. Field of the Invention
This invention relates to a video signal processing apparatus including a time base corrector for correcting fluctuations in a video signal reproduced from a recording medium and a video signal processing circuit for processing an output video signal from the time base corrector.
2. Description of the Prior Art
A conventional time base corrector converts an input video signal using an A/D converter to a digital signal, writes the digital signal into a memory operated using a write-in clock signal, reads the written signal from the memory using a standard clock, and converts the read-out signal back to its analog form. The write-in clock signal is synchronized with a horizontal synchronizing signal or color burst signal carried in the input video signal and contains a phase shift equivalent to a time base error in either the horizontal synchronizing signal or color burst signal. The detection of the time base error in the horizontal synchronizing or color burst signal is executed during a horizontal scanning period. Accordingly, a time base error within one horizontal scanning period is not corrected and remains as a velocity error.
For compensation for the velocity error, the read-out clock signal is phase modulated corresponding to a velocity error data fed from the write-in clock signal generating circuit and used for reading from the memory a desired data that is in turn converted to an analog form for output. Such an apparatus is disclosed in the form of a time base corrector in the U.S. Pat. No. 4,165,524. In the apparatus, the phase shift of the read-out clock signal is determined in proportion to a video data to be retrieved and hence the video data has to be converted to an analog form immediately after being read out from the memory with the read-out clock signal.
Accordingly, when signal processing is carried out with respect to time delays or continuation errors in the time base between the memory and D/A converter, a timing error occurs between the video data to be D/A converted and the velocity error data to be used for phase modulation of the read-out clock signal. For example, a timing error will likely occur during edge enhancement with the use of a line memory or reproduction of a still picture with field or frame memories. As a result, the velocity error can be no longer be compensated but is instead ironically enhanced.
Also, the processing of signals read from the memory through an arithmetic operation including in-line and in-field calculation involves computation of video signals having different velocity errors. Hence, the velocity error itself becomes different from the one before the arithmetic operation. In addition to the timing between the velocity error and the video data, another problem arises in that video data released from a calculating circuit fails to correspond to the velocity error data and thus, no exact compensation for the velocity error will be executed.
To solve the above problems, the present inventors proposed a method of superposing velocity error data within a horizontal synchronizing signal period of video signal. This method is disclosed in the U.S. patent application Ser. No. 07/712,041, filed Jun. 7, 1191. A velocity error is superposed as residual error data on the horizontal synchronizing signal of the video signal possessing the velocity error, and the signal having a time delay or discontinuity in the time axis is processed together with the video signal, and then the residual error data is taken out from the horizontal synchronizing signal of the video signal, so that the velocity error may be obtained which corresponds to the video signal to be D/A converted.
However, with the residual error data superposed in the horizontal synchronizing signal period, the horizontal synchronization is disturbed in the monitor receiver, and a normal image is not obtained.